In the field of integrated circuit devices, power gating or power shut-off is an effective method of leakage power reduction for functional units that have a burst-like application profile. For example, during a ‘not-in-use’ state for such a functional unit, a power or ground supply of the functional unit may be gated, e.g. de-coupled, using an on-die gating switch, such as a large PMOSFET or NMOSFET (p-channel/n-channel metal oxide semiconductor field effect transistor) in triode mode.
A problem associated with such power gating techniques involves a significant rush of current drawn by the circuitry when the functional unit is subsequently un-gated, i.e. re-coupled to the power or ground supply. This rush of current is, to a large extent due to the charging of parasitic and explicit device capacitances within the circuitry of the functional unit. Such a large rush of current can have a significant and detrimental effect on neighbouring circuits connected to the same power/ground supply. Thus, it is generally desirable to minimise the current drawn by the circuitry when a functional unit is subsequently un-gated.
However, the power-up time for a functional unit depends on the capacitance to be charged and the charge current amplitude. Accordingly, restricting the charge current available when a functional unit is un-gated can also result in the power gating recovery for the functional unit taking longer, reducing the efficiency of the power gating process.